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This work presents a Phase Lock Loop for Carrier Wave (CPLL) and a Phase Lock Loop for Data Bits (DPLL). Each one of these devices is constituted by a phase comparator, a loop gain, a low pass filter and a voltage controlled oscillator. The objective is to study these synchronizers and evaluate their performance in presence of noise. We measure the output jitter UIRMS (Unit Intervals Root Mean Square) versus input SNR (Signal Noise Ratio).
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Synchronism Digital Communication Systems