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Abstract(s)
Ao longo do trabalho desenvolvido estudou-se a arquitectura de quatro dos sistemas de detecĆ§Ć£o de fase existentes na literatura e que historicamente apresentam um impacto evolutivo nesta Ć”rea, o sistema Detector de Passagem por Zero (Zero Cross Detector-ZCD), o sistema Ciclo de Procura de Fase (Phase Lock Loop-PLL), o sistema PLL com Filtro Rejeita Banda (Notch Filter PLL ā NPLL) e o sistema SOGI-PLL (Second Order Generalized IntegratorāPLL). Foram analisadas as fragilidades existentes em cada uma das tecnologias estudadas e que serviram de base para que estes algoritmos fossem evoluindo ao longo dos anos, muito em funĆ§Ć£o das necessidades e especificidades encontradas. Procedeu-se ao desenvolvimento matemĆ”tico de cada um dos algoritmos e, posteriormente, Ć sua implementaĆ§Ć£o, para simular os perfis de resposta, no programa MatlabĀ®.
Para base de teste dos algoritmos em estudo, fez-se o dimensionamento de uma interface electrĆ³nica para aquisiĆ§Ć£o e modulaĆ§Ć£o do sinal de tensĆ£o da rede real tendo em conta as necessidades de isolamento e seguranƧa. Fez-se ainda um estudo da arquitectura e funcionamento do microcontrolador em uso e, em funĆ§Ć£o desses parĆ¢metros, desenvolveu-se o cĆ³digo numa linguagem compatĆvel e testaram-se os diferentes algoritmos.
Along the development of this work it was possible to look at the architecture of four phase detector processes that can easily be found in literature and which represent the one with the most impact on this field of study, the Zero Cross Detector (ZCD), the Phase Lock Loop (PLL), the PLL with a Noch Filter (NPLL) and the Second Order Generalized Integrator (SOGI-PLL). As new requirements and specifications arose, the study of the weaknesses of each of these architectures allowed for the improvement of the algorithms over time. A mathematical study allowed for the creation of models that could be implemented on MatlabĀ® permitting the testing of the algorithms in order to highlight the differences between each of their responses. To simulate the behavior of the algorithms on an environment closer to the ones they are designed for, an electronic platform capable of acquiring and modulating the grids signal was designed and developed taking into account isolation and security measures. This dissertation also includes a study on the architecture and operation of the microcontroller, the details on programming the device and the testing of the different algorithms in a close to reality environment.
Along the development of this work it was possible to look at the architecture of four phase detector processes that can easily be found in literature and which represent the one with the most impact on this field of study, the Zero Cross Detector (ZCD), the Phase Lock Loop (PLL), the PLL with a Noch Filter (NPLL) and the Second Order Generalized Integrator (SOGI-PLL). As new requirements and specifications arose, the study of the weaknesses of each of these architectures allowed for the improvement of the algorithms over time. A mathematical study allowed for the creation of models that could be implemented on MatlabĀ® permitting the testing of the algorithms in order to highlight the differences between each of their responses. To simulate the behavior of the algorithms on an environment closer to the ones they are designed for, an electronic platform capable of acquiring and modulating the grids signal was designed and developed taking into account isolation and security measures. This dissertation also includes a study on the architecture and operation of the microcontroller, the details on programming the device and the testing of the different algorithms in a close to reality environment.
Description
Keywords
Algoritmos de SincronizaĆ§Ć£o Com A Rede (Grid Synchronization Algorithms) Ciclo de Procura de Fase (Phase Lock Loop-Pll) Detector de Fase (Phase Detector-Pd) Integrador de Segunda Ordem (Second Order Generalized Integrator-Sogi).